1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved structure and method for producing electrically programmable read only memory devices (EPROM's) and flash EPROM's devices.
2) Description of the Prior Art
In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large increase due to the rapid growth of digital electronics market with multiplying applications. Moreover, flash electrically programmable read only memories devices (flash EPROM's) are being produced in larger quantities. Lately, high density flash memory has been expected to replace some part of the large computer external storage device market. One of the goals in the fabrication of flash electrically programmable read only memories (flash EPROM's) is the production of a memory circuit that is capable of storing a maximum amount of information using a minimum amount of semiconductor surface area. However, photolithographic limits imposed by conventional semiconductor processing technology impede the achievement of this goal. Thus, the inability to pattern and etch semiconductor features closed together prevents a memory cell from occupying a smaller portion of a semiconductors surface. Another goal of flash EPROM manufacturing is use of a simple cheap high yielding process. Many previous methods to reduce device size add too much complexity and cost.
Flash EPROMs frequently use a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure to store information. Floating gate dimensions in a FAMOS memory cell are conventionally established with reference to minimum photolithographic limits and therefore produce undesirable large memory cells. A conventional configuration for an EPROM device is the stacked gate structure as shown in FIG. 1. Source 12 and Drain 14 regions are formed in substrate 10. The floating gate 16 overlies the channel region, the area between the source and drain. The control gate 18 overlays the floating gate 16. An insulating structure 20 insulates the substrate, floating gate and control gate. The minimum size of the conventional stack gate structure is determined by the photolithographic limits which determine the floating gate, control gate, source and drain widths.
A less than optimal solution to this problem of sizing the floating gate at minimum photolithographic limits is provided by the use of a side wall floating gate formed on a sidewall of a control gate. However, since the floating gate is merely added to a sidewall of a photolithographic defined control gate, the resulting structure is actually larger than a structure achievable at minimum photolithographic limits. In addition, it provides an undesirable diminished capacitive coupling between the floating gate and the control gate. Accordingly, a need exists for a memory cell in which a floating gate structure is provided with dimension less than minimum photolithographic limits, but which is not formed on a sidewall of a control gate.
A method of producing an EPROM having sidewall floating gates that seeks to reduce cell size is shown in U.S. Pat. No. 5,143,860. Floating gates are formed on the sidewalls of oxide layers overlying the source and drain regions. A control gate layer overlies two adjacent floating gates. This method produces EPROM cells smaller than that achievable using conventional the photolithographic limited stacked gate structure. However, this cell has the limitation of a small control gate to floating gate contact area which reduces the capacitive coupling which in turn makes the floating gate less responsive to voltage charges from the control gate. More importantly, this method is not the optimal solution and a need for a smaller cell structure still exists.